One embodiment of the invention relates to a semiconductor apparatus comprising a memory, and more particularly to a semiconductor apparatus having an incorporated self-test and a method of testing a failure analysis of the memory through the incorporated self-test.
The number of memories to be loaded onto a system large scale integrated circuit (LSI) reaches several tens to several hundreds, and most of the memories have been tested by an incorporated self-test (BIST: Built in Self Test) Irrespective of the presence of the BIST, there is no change in a flow in which the failure is analyzed to investigate the cause of the failure and a countermeasure is taken when a failure is found in the memory. A fail bit map (FBM) is the most effective for the failure analysis of the memory.
In the case in which access is directly given to the memory by using a normal memory tester to carry out a test, an FBM acquirement is very easy. The same address space as a memory to be measured is mapped into a failure analyzing memory in the tester and a result of the test for each cell is stored in the failure analyzing memory synchronously with the test. A general memory tester has the mapping function standardly.
On the other hand, the FBM acquirement of the memory subjected to the BIST is very complicated. In a test mode using the normal BIST, an output of the memory is compared with an expected value in a BIST circuit and only a result thereof is output to an external pin.
For example, in a basic operation in the test mode through the BIST, an address signal, a memory control signal and write data are input from the BIST circuit to each of a plurality of memory circuits, and writing and reading operations are carried out for the memory of the memory circuit. Data read from the memory are input to a comparator via a data register in the memory circuit and are compared with the expected value output from the BIST circuit. In the BIST circuit, a logical sum of the comparison results of the memories is output as a test result.
For the FBM acquirement, it is necessary to know an address of a memory cell having a failure. Even if a result of quality of the memory can be acquired in an operation in the test mode of the memory BIST, however, it is impossible to acquire an address of a defective cell. In order to obtain the address of the defective cell, a BIST having a failure analyzing mode is present in addition to a normal test mode.
In a general failure analyzing mode, failure analysis data read from the memory are output to the external pin through a shift chain path. For example, failure analysis data corresponding to one address which are read from the cell of the memory are once stored in the data register. The data register of each memory circuit is connected like a shift register through the shift chain path, and the failure analysis data are successively output from the BIST circuit to an external output pin through a shift-out operation. By comparing output data with the expected value over the tester, it is possible to detect the failure. An address of a defective cell is led from a failure detecting step, and an FBM is created to carry out the failure analysis for the memory. A relationship between the failure detecting step and the defective address can be obtained from a size of the memory to be measured and a test specification of the BIST.
In a general failure analyzing mode, a timing chart including a shift-out step after the reading step is used. Therefore, it is possible to output the failure analysis data on the memory to an outside and to acquire the FBM of the memory subjected to the BIST. However, the shift-out operation for the failure analysis data read after the failure analysis data are read from the memory is carried out. Therefore, an operation for carrying out write to the memory cannot be immediately started and it is impossible to give continuous access to the memory. For this reason, the memory is not tested at an actual specification frequency.
The cause of the failure of the memory is not restricted to a physical open/short circuit. For example, a failure caused by a parasitic capacitance or a parasitic resistance can be detected by only a high-speed test in many cases. Accordingly, it is necessary to test the memory at the actual specification frequency.
There has been proposed a failure analyzing mode for testing a memory at an actual specification speed by using a BIST (for example, see Patent Documents JP-A-2002-298598 and JP-A-2004-86996). In the failure analyzing mode which has been proposed, failure analysis data output at a high speed are stored in a memory for an FBM which is provided separately from or provided in a semiconductor apparatus in order to hold a test result. After the end of the test, the failure analysis data which are stored are processed by a low-speed tester to create the FBM. In the Patent Document JP-A-2002-298598, however, the failure analysis data which are read are successively output to the memory for the FBM. For this reason, it is impossible to carry out the write to the memory immediately after the reading operation. In the Patent Document JP-A-2004-86996, when a defective bit is detected, an operation for reading a next address is stopped for a certain clock number period. Even if the memory is tested by using a clock having an actual specification in the failure analyzing mode, accordingly, an actual memory test is partially interrupted. In the failure analyzing mode, therefore, it is hard to output the failure analysis data while testing the memory at the actual specification frequency.